As computers advance, integration of platforms and their components become a larger and more complex task. As devices within computers continue to evolve, the speed at which the devices internally run increases. To this end, interconnects between devices become a limiting performance factor, if the speed at which interconnects transmit data is not increased. Previously, interconnects at much slower speeds were more concerned with the digital design of the output buffer, as compared to the integrity of signals transmitted.
However, as speeds of transmitted signals on interconnects have progressed from MHz to GHz, the need for better signal integrity has become essential. As the frequency of transmitted signals continue to increase, timing and signal integrity become important in ensuring that valid and correct data is transmitted. Yet, as the transmission speed of data has increased, the speed at which data must be processed and output onto interconnects has also increased.
As a consequence, data pre-processing activities have been split into lower speed parallel path in order to efficiently execute complex logical and arithmetic operations. For example, computation equalization of an output data stream may be difficult at a full output rate. However, by splitting operations into the parallel paths the eventual merger of the data stream in a differential driver will quickly consume any allowable output jitter budget due to systematic imperfection in the output data time alignment.